A Combined Sdc-sdf Architecture for Normal I/o Pipelined

Fast Fourier transform (FFT) has played a significant role in digital signal processing field, especially in the advanced communication systems, such as orthogonal frequency division multiplexing (OFDM) and asymmetric digital subscriber line. An efficient combined single-path delay commutator-feedback (SDC-SDF) radix-2 pipelined fast Fourier transform architecture, which includes log 2 − 1 SDC stages, and 1 SDF stage. The SDC processing engine is proposed to achieve 100% hardware resource utilization by sharing the common arithmetic resource in the time-multiplexed approach, including both adders and multipliers. Thus, the required number of complex multipliers is reduced in the proposed architecture, compared with the existing radix-2 SDC/SDF architectures. In addition, the proposed architecture requires roughly minimum number of complex adders and complex delay memory. The proposed architecture is coded using HDL and the code is simulated using ModelSim tool. The proposed architecture code is synthesized using Xilinx CAD tool.